Space invaders repair - Revision history

Mahjongg: /* 11/11/2019 Done a course on CRT repair, and now know how to fix the CRT */

2019-11-11T10:34:12Z

11/11/2019 Done a course on CRT repair, and now know how to fix the CRT

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	== 11/11/2019 Done a course on CRT repair, and now know how to fix the CRT ==		== 11/11/2019 Done a course on CRT repair, and now know how to fix the CRT ==
	The arcade cabinet repair course I did from Randy Fromm has ~~bared~~ me some knowledge, and I now know how to fix the monitor.		The arcade cabinet repair course I did from Randy Fromm has given me some knowledge, and I now know how to fix the monitor.
	Also I have build a component tester that can use to test the ESR (equivalent series resistance) of an electrolytic capacitor to check if it has dried out (one of the most important failure modes that happen in arcade cabinets that are several decades old.		Also I have build a component tester that can use to test the ESR (equivalent series resistance) of an electrolytic capacitor to check if it has dried out (one of the most important failure modes that happen in arcade cabinets that are several decades old.

Mahjongg: /* Drawn the schematic of the pseudo noise generator */

2019-11-11T10:33:34Z

Drawn the schematic of the pseudo noise generator

← Older revision		Revision as of 10:33, 11 November 2019
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	Don’t know how to fix that, besides exchanging all the capacitors in the CRT logic pcb.		Don’t know how to fix that, besides exchanging all the capacitors in the CRT logic pcb.

			== 11/11/2019 Done a course on CRT repair, and now know how to fix the CRT ==
			The arcade cabinet repair course I did from Randy Fromm has bared me some knowledge, and I now know how to fix the monitor.
			Also I have build a component tester that can use to test the ESR (equivalent series resistance) of an electrolytic capacitor to check if it has dried out (one of the most important failure modes that happen in arcade cabinets that are several decades old.

Mahjongg: /* Drawn the schematic of the pseudo noise generator */

2019-11-03T00:33:06Z

Drawn the schematic of the pseudo noise generator

← Older revision		Revision as of 00:33, 3 November 2019
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	However I learned that the CD4006 will arrive soon, so I don't need to design the replacement circuit.		However I learned that the CD4006 will arrive soon, so I don't need to design the replacement circuit.

			In the end the CD4006 did indeed arrive, and the random generator worked, and brought explosion sounds back, but it seems there is still something missing, namely the “droning” sound

			In the mean time it has become more and more difficult to get the console out of reset, it often takes many attempts before it will start, the suspect is the power good reset circuit on the power supply board, but all attempts to fix the supply have failed to make a difference,and now the CRT seems to develop problems, resulting in a distorted and rolling picture.

			Don’t know how to fix that, besides exchanging all the capacitors in the CRT logic pcb.

Mahjongg at 00:22, 3 November 2019

2019-11-03T00:22:00Z

Mahjongg at 00:09, 3 November 2019

2019-11-03T00:09:17Z

← Older revision		Revision as of 00:09, 3 November 2019
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	As I suspected the CPU, the intel 9316 ROM's or the 2107 RAMs (which are notoriously unreliable, as one was obviously already replaced in the past) could be defective, I needed a known good test-ROM to test them, unfortunately the system uses old intel mask ROMs (not even EEPROM's) which are also prone to get bad, but the schematic noted that 2716 EEPROMS could be used instead, and provided some very sketchy re-jumpering pictures (but note that you should NOT trust these, they are IMHO incredibly difficult to decipher, and also WRONG).		As I suspected the CPU, the intel 9316 ROM's or the 2107 RAMs (which are notoriously unreliable, as one was obviously already replaced in the past) could be defective, I needed a known good test-ROM to test them, unfortunately the system uses old intel mask ROMs (not even EEPROM's) which are also prone to get bad, but the schematic noted that 2716 EEPROMS could be used instead, and provided some very sketchy re-jumpering pictures (but note that you should NOT trust these, they are IMHO incredibly difficult to decipher, and also WRONG).
	Problem is that four 2716 EEPROMs these days are almost impossible to get hold of, but I did find a 27C64, which in theory could replace all four, in principle I only needed one 2716 for the (original) RAM test code, the one that would write a single digit to RAM in the middle of the screen, hoping that enough of the RAM's would be working so you could actually recognise the digit. In the end [[benadski]] found a much more involved test ROM, which did much more than that, but used all four 2K regions ~~(for~~ 2716's), and we programmed this into the 2764 taking care to write the first of the four test roms (test.h) in the lowest of the four locations in the ROM, and test.g test.f and test.e in the succeeding ones, aso as to create one blok of 8K code.		Problem is that four 2716 EEPROMs these days are almost impossible to get hold of, but I did find a 27C64, which in theory could replace all four, in principle I only needed one 2716 for the (original) RAM test code, the one that would write a single digit to RAM in the middle of the screen, hoping that enough of the RAM's would be working so you could actually recognise the digit. In the end [[benadski]] found a much more involved test ROM, which did much more than that, but used all four 2K regions four 2716's), and we programmed this into the 2764 taking care to write the first of the four test roms (test.h) in the lowest of the four locations in the ROM, and test.g test.f and test.e in the succeeding ones, aso as to create one blok of 8K code.
	Initially I thought that [[benadski]] had used the old 2K test and did not understand why he had written four files to the ROM, but once I saw a screenshot of the testrom in action I realised what I had.		Initially I thought that [[benadski]] had used the old 2K test and did not understand why he had written four files to the ROM, but once I saw a screenshot of the testrom in action I realised what I had.

Mahjongg at 00:04, 3 November 2019

2019-11-03T00:04:39Z

← Older revision		Revision as of 00:04, 3 November 2019
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	This describes the vicissitudes I experienced while attempting this feat.		This describes the vicissitudes I experienced while attempting this feat.

	Note this isn't actually a RevSpace project, (as all the work is ~~none~~ at the Awesomespace location in Utrecht) but I still thought it was note worthy to document my experiences somewhere, as actual information is hard to come by.		Note this isn't actually a RevSpace project, (as all the work is done at the Awesomespace location in Utrecht) but I still thought it was note worthy to document my experiences somewhere, as actual information is hard to come by.

	The symptoms of the problem were that the console when turned on only displayed a screen full of "garbage", that is, a screen filled with a repeating pattern of seeming random pixels repeating something like eight times over the screen, with no discernible motion in this pixels.		The symptoms of the problem were that the console when turned on only displayed a screen full of "garbage", that is, a screen filled with a repeating pattern of seeming random pixels repeating something like eight times over the screen, with no discernible motion in this pixels.

Mahjongg: /* 23 september 2017 replaced the last LM3900 */

2019-11-01T11:01:02Z

23 september 2017 replaced the last LM3900

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	== 23 september 2017 replaced the last LM3900 ==		== 23 september 2017 replaced the last LM3900 ==
	Yeah, I replaced the one remaining LM3900 with a new one, and also replaced the one CD4016 analog switch chip that was in the system with a more modern replacement the CD4066.		Yeah, I replaced the one remaining LM3900 with a new one, and also replaced the one CD4016 analog switch chip that was in the system with a more modern replacement the CD4066.
	It made no discernible difference. I added GND and +5V points to connect a test probe, and looked at the noise generator, but I found no noise, as the noise output was always low. Also the oscillator for the digital noise generators clock signal was always low, so I suspect the CD4030 XOR ports chip to be defective, and not generating a clock signal for the 4006 shift register. Perhaps i can still find a CD4030, finding a CD4006 ( a long chain of shift registers ) will be far more difficult to find, and it might not be broken. P..s in hindsight I should have powered the probe with 12V, not 5V as I did, as now its results might no be reliable, but yes a 12V high would certainly be seen as a high, so I guess it doesn't matter.		It made no discernible difference. I added GND and +5V points to connect a test probe, and looked at the noise generator, but I found no noise, as the noise output was always low. Also the oscillator for the digital noise generators clock signal was always low, so I suspect the CD4030 XOR ports chip to be defective, and not generating a clock signal for the 4006 shift register. Perhaps i can still find a CD4030, finding a CD4006 ( a long chain of shift registers ) will be far more difficult to find, and it might not be broken. P..s in hindsight I should have powered the probe with 12V, not 5V as I did, as now its results might not be reliable, but yes a 12V high would certainly be seen as a high, so I guess it doesn't matter.
	So I still I expect the CD4030 to be defective, at least its certainly the pseudo random noise generator that is not working, as its the reason why explosions (sort bursts of noise) do not work, and why player firing sounds strange, as both use the noise from the random generator.		So I still I expect the CD4030 to be defective, at least its certainly the pseudo random noise generator that is not working, as its the reason why explosions (sort bursts of noise) do not work, and why player firing sounds strange, as both use the noise from the random generator.
	Ill try to find a CD4030, or a replacement.		Ill try to find a CD4030, or a replacement.

Mahjongg: /* Drawn the schematic of the pseudo noise generator */

2017-11-13T16:07:25Z

Drawn the schematic of the pseudo noise generator

← Older revision		Revision as of 16:07, 13 November 2017
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	The other two XOR's are used as an inverter and a buffer, which form an oscillator which generates the clock for the shift registers.		The other two XOR's are used as an inverter and a buffer, which form an oscillator which generates the clock for the shift registers.

	I will ~~draw a simplified drawing of~~ the ~~register chain~~.		This is the simplified schematic diagram:
			[[File:Simplified pseudo random generator.png\|500px]]

			However I learned that the CD4006 will arrive soon, so I don't need to design the replacement circuit.

Mahjongg: /* Drawn the schematic of the pseudo noise generator */

2017-11-10T22:29:42Z

Drawn the schematic of the pseudo noise generator

← Older revision		Revision as of 22:29, 10 November 2017
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	The circuits uses a chain of 4 + 5 + 4 + 4 = 17 shift registers, one stage isn't used, as isn't the latch.		The circuits uses a chain of 4 + 5 + 4 + 4 = 17 shift registers, one stage isn't used, as isn't the latch.

	If we (arbitrarily) take pin 10 as the logical end of the shift register chain, then if we work back we see 4 + 4 = 8 stages before a node occurs with a branch to an XOR, then going further back we see 5 stages before we get to the "input" (D2) consisting of a ~~power on/~~XOR output circuit. This circuit produces either a duration of "logic highs" during power on, or ~~later~~ the output of the XOR. So we can see that initially the shift register chain is filled with "1"'s, to initialise it to a know state, and later with the result of the XOR.		If we (arbitrarily) take pin 10 as the logical end of the shift register chain, then if we work back we see 4 + 4 = 8 stages before a node occurs with a branch to an XOR, then going further back we see 5 stages before we get to the "input" (D2) consisting of a "initialisation & XOR output" circuit. This circuit produces either a duration of "logic highs" during power on, or after that the output of the XOR. So we can see that initially the shift register chain is filled with "1"'s, to initialise it to a know state, and later it is filled with the result of the XOR.

	The end of the chain (pin-10, the noise output) goes on to another 4 stages, before reaching the other XOR input. Its this XOR which produces the pseudo random stream of 1's and 0's from the two input signals.		The end of the chain (pin-10, the noise output) goes on to another 4 stages, before reaching the other XOR input. Its this XOR which produces the pseudo random stream of 1's and 0's from the two input signals.

Mahjongg: /* Drawn the schematic of the pseudo noise generator */

2017-11-10T22:25:39Z

Drawn the schematic of the pseudo noise generator

← Older revision		Revision as of 22:25, 10 November 2017
Line 144:		Line 144:
	The circuits uses a chain of 4 + 5 + 4 + 4 = 17 shift registers, one stage isn't used, as isn't the latch.		The circuits uses a chain of 4 + 5 + 4 + 4 = 17 shift registers, one stage isn't used, as isn't the latch.

	If we (arbitrarily) take pin 10 as the logical end of the shift register chain, then if we work back we see 4 + 4 = 8 stages before a node occurs with a branch to an XOR, then going further back we see 5 stages before we get to the "input" (D2) consisting of a power on/XOR output circuit. This circuit produces either a duration of "logic highs" during power on, or later the output of the XOR. So we can see that initially the shift register chain is filled with "1"'s, and later with the result of the XOR.		If we (arbitrarily) take pin 10 as the logical end of the shift register chain, then if we work back we see 4 + 4 = 8 stages before a node occurs with a branch to an XOR, then going further back we see 5 stages before we get to the "input" (D2) consisting of a power on/XOR output circuit. This circuit produces either a duration of "logic highs" during power on, or later the output of the XOR. So we can see that initially the shift register chain is filled with "1"'s, to initialise it to a know state, and later with the result of the XOR.

	The end of the chain (pin-10, the noise output) goes on to another 4 stages, before reaching the other XOR input. Its this XOR which produces the pseudo random stream of 1's and 0's from the two input signals.		The end of the chain (pin-10, the noise output) goes on to another 4 stages, before reaching the other XOR input. Its this XOR which produces the pseudo random stream of 1's and 0's from the two input signals.

← Older revision		Revision as of 00:22, 3 November 2019
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	As I suspected the CPU, the intel 9316 ROM's or the 2107 RAMs (which are notoriously unreliable, as one was obviously already replaced in the past) could be defective, I needed a known good test-ROM to test them, unfortunately the system uses old intel mask ROMs (not even EEPROM's) which are also prone to get bad, but the schematic noted that 2716 EEPROMS could be used instead, and provided some very sketchy re-jumpering pictures (but note that you should NOT trust these, they are IMHO incredibly difficult to decipher, and also WRONG).		As I suspected the CPU, the intel 9316 ROM's or the 2107 RAMs (which are notoriously unreliable, as one was obviously already replaced in the past) could be defective, I needed a known good test-ROM to test them, unfortunately the system uses old intel mask ROMs (not even EEPROM's) which are also prone to get bad, but the schematic noted that 2716 EEPROMS could be used instead, and provided some very sketchy re-jumpering pictures (but note that you should NOT trust these, they are IMHO incredibly difficult to decipher, and also WRONG).
	Problem is that four 2716 EEPROMs these days are almost impossible to get hold of, but I did find a 27C64, which in theory could replace all four, in principle I only needed one 2716 for the (original) RAM test code, the one that would write a single digit to RAM in the middle of the screen, hoping that enough of the RAM's would be working so you could actually recognise the digit. In the end [[benadski]] found a much more involved test ROM, which did much more than that, but used all four 2K regions four 2716's), and we programmed this into the 2764 taking care to write the first of the four test roms (test.h) in the lowest of the four locations in the ROM, and test.g test.f and test.e in the succeeding ones, ~~aso~~ as to create one blok of 8K code.		Problem is that four 2716 EEPROMs these days are almost impossible to get hold of, but I did find a 27C64, which in theory could replace all four, in principle I only needed one 2716 for the (original) RAM test code, the one that would write a single digit to RAM in the middle of the screen, hoping that enough of the RAM's would be working so you could actually recognise the digit. In the end [[benadski]] found a much more involved test ROM, which did much more than that, but used all four 2K regions four 2716's), and we programmed this into the 2764 taking care to write the first of the four test roms (test.h) in the lowest of the four locations in the ROM, and test.g test.f and test.e in the succeeding ones, so as to create one blok of 8K code.
	Initially I thought that [[benadski]] had used the old 2K test and did not understand why he had written four files to the ROM, but once I saw a screenshot of the testrom in action I realised what I had.		Initially I thought that [[benadski]] had used the old 2K test and I did not understand why he had written four files to the ROM, but once I saw a screenshot of the testrom in action I realised what I had.

	[[File:Space invaders test.jpg]]		[[File:Space invaders test.jpg]]
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	Still the EEPROM did not work, and in the meantime I discovered that I had an 8K testrom not a 2K testrom, so I had satisfied the EEPROM by adding address lines A11 and A12,		Still the EEPROM did not work, and in the meantime I discovered that I had an 8K testrom not a 2K testrom, so I had satisfied the EEPROM by adding address lines A11 and A12,
	While measuring all the pins of the EEPROM one by one (which previously had given me the insight that the "2716 jumping scheme" was completely wrong as the right signals did not end up on the right EEPROM pins, and one address pin even had 12V on it :-( , so I completely rewired the ~~jumping~~) I found out that pin 20 (Output enable) wasn't used at all! all the pin 20 pins of all eight sockets were connected together, but NOTHING was driving the /OE pin! So I wired it to A14, meaning the EEPROM would output actual data if any one of the first four roms were addressed, but tying it simply low would have worked also I think.		While measuring all the pins of the EEPROM one by one (which previously had given me the insight that the "2716 jumping scheme" was completely wrong as the right signals did not end up on the right EEPROM pins, and one address pin even had 12V on it :-( , so I completely rewired the jumpering) I found out that pin 20 (Output enable) wasn't used at all! all the pin 20 pins of all eight sockets were connected together, but NOTHING was driving the /OE pin! So I wired it to A14, meaning the EEPROM would output actual data if any one of the first four roms were addressed, but tying it simply low would have worked also I think.

	I was rewarded with a changed picture, instead of the "good vertical lines" picture I got a picture of either all even or all odd pixel rows being shown, alternating once every second or so.		I was rewarded with a changed picture, instead of the "good vertical lines" picture I got a picture of either all even or all odd pixel rows being shown, alternating once every second or so.
	I still have no clue what this means, perhaps the documentation of the new testrom has something to say, or otherwise I have to use a logic analyser to see if the i8080 ~~get~~ the right EEPROM data, fortunately we seem to have just such a logic analyser at Awesome space, and old one, but it seems to work, although no one has used it yet. my latest idea as to what might be wrong, is that one of the data-bus multiplexers is bad, or it could be that the line pattern points to something specific, explained in test rom documentation.		I still have no clue what this means, perhaps the documentation of the new testrom has something to say, or otherwise I have to use a logic analyser to see if the i8080 got the right EEPROM data, fortunately we seem to have just such a logic analyser at Awesome space, and old one, but it seems to work, although no one has used it yet. my latest idea as to what might be wrong, is that one of the data-bus multiplexers is bad, or it could be that the line pattern points to something specific, explained in test rom documentation.
	interestingly this video of a space invaders console booting this same testrom shows the exact same vertical lines I get, but then continues with other (RAM testing) patterns, this might mean that part of the boot rom is executed, but then crashes. https://www.youtube.com/watch?v=jLM_LJ-QgdE		interestingly this video of a space invaders console booting this same testrom shows the exact same vertical lines I get, but then continues with other (RAM testing) patterns, this might mean that part of the boot rom is executed, but then crashes. https://www.youtube.com/watch?v=jLM_LJ-QgdE

	== May 5, 2017 ITS ALIVE! ==		== May 5, 2017 ITS ALIVE! ==

	Yes, there is live in the old thing! I managed to get the testprogram working, initially it was bit of touch and go, sometimes (about one in forty attempts) it started, but most of the time I only got vertical lines, but after long a work on it, I managed to get the program to start consistently, with a press on a reset button I added, and with power-on-reset tied low with a 470 Ohm resistor.		Yes, there is live in the old thing! I managed to get the testprogram working! initially it was bit of touch and go, sometimes (about one in forty attempts) it started, but most of the time I only got vertical lines, but after long a work on it, I managed to get the program to start consistently, with a press on a reset button I added, and with power-on-reset tied low with a 470 Ohm resistor.
	here is the proof:		here is the proof: